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Interested in having your device fabricated and tested?
We are offering a free fabrication/test service, OpenEBL, for a small design area of 605 µm x 410 µm, to our international family of designers who are familiar with our EBeam process. The purpose is to allow people who have taken our courses or workshops to obtain fabrication & testing. We typically perform our fabrication/test runs 3 times per year.
The OpenEBL project is a SiEPICfab activity enabled by the contribution of its members. Design tools used are provided by free, open-source tools such as SiEPIC EPDA (SiEPIC-Tools and SiEPIC EBeam PDK) as well as Luceda (ipkiss). Fabrication is provided by Applied Nanotools and University of Washington. Measurements are done by SiEPICfab using Maple Leaf Photonics measurement probe stations. Test and measurement instruments by Keysight Technologies.
OpenEBL Run Schedule
| Run ID | Design Due Date |
| OpenEBL-23-01 | Friday February 17, 2023 |
| OpenEBL-23-02 | Friday May 13, 2023 |
| OpenEBL-23-03 | Friday October 20, 2023 |
Fabrication
- 100keV Electron Beam Lithography at the University of Washington and/or Applied Nanotools Inc.
- 220 nm SOI
- Passive-only process, with a single etch.
- Layers: 1 = silicon, 10 = text label for automated measurements; 99 = floorplan.
- Design area: 605 µm x 410 µm
Testing
- Provided by the SiEPIC program; testing located at The University of British Columbia using Maple Leaf Photonics probe stations.
- Automated test using a fibre array: 1 input [on Fibre 2], 3 outputs [on Fibres 1, 3, 4]; transmission spectra near 1550 nm and 1310 nm.
- TE and/or TM polarization
Fabrication process details and tutorials
- SiEPIC EBeam PDK (please read the repository home page)
- edX online course
- SiEPIC courses and workshops
Submission
- Filename – EBeam_openEBL_USERNAME.gds – “openEBL” is case sensitive; replace USERNAME with your name. Append “_A”, “_B”, etc., if submitting multiple layouts.
- Top cell name – EBeam_openEBL_USERNAME
- Design must be made using the SiEPIC EBeam PDK
- Template layout
- Use measurement label opt_in_[pol]_[wavelength]_openEBL_[yourname]_[deviceID]
- [pol] being the polarization (TE or TM)
- [wavelength] being the wavelength band of your device (1550 or 1310)
- [yourname] A unique username for you to identify your data
- [deviceID] being the device identifier, you can further underscores there as well.
- Example: opt_in_TE_1310_openEBL_maxwell_RingResonator_gap_100nm
- [pol] = TE
- [wavelength] = 1310
- [yourname] = maxwell
- [deviceID] = RingResonator_gap_100nm
- Upload your GDS layout file below:
Fabrication Results
- Results will be shared via:
- Disclaimer: Nothing is guaranteed. Provided as-is, best effort. The designs submitted here are publicly accessible. For educational purposes. Space limited; first-come first-served.
- If your design does not make it on this tape-out, it is likely because the chip is full. Do not resubmit your design. Your previously submitted design will be first in line for the next fabrication run.
Online community
- Join the SiEPIC LinkedIn group to keep up on the latest news and events
- Join the SiEPIC newsletter to stay up to date on upcoming runs and measurement results